On-chip interconnect inductance - Friend or foe (invited)

被引：7

作者：

Wong, SS ^{[1
]}

Yue, P ^{[1
]}

Chang, R ^{[1
]}

Kim, SY ^{[1
]}

Kleveland, B ^{[1
]}

O'Mahony, F ^{[1
]}

机构：

[1] Stanford Univ, Ctr Integrated Syst, Stanford, CA 94305 USA

来源：

4TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/ISQED.2003.1194764

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

Inductance associated with on-chip wires can no longer be ignored as chip operation frequencies increase into GHz regime. Because the magnetic field propagates a very long range, the extraction of wire inductance is not just dependent on the immediate neighboring environment. This paper discusses the various difficulties of extracting inductance of randomly placed wires in a typical chip environment. With dedicated return path, the wire inductance can be controlled and benefit the design of high-speed circuits. Specific examples are illustrated.

引用

页码：389 / 394

页数：6

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