On-chip self-calibrating communication techniques robust to electrical parameter variations

被引：5

作者：

Worm, F

Ienne, P

Thiran, P

De Micheli, G

机构：

[1] Swiss Fed Inst Technol, CH-1015 Lausanne, Switzerland

[2] Stanford Univ, Stanford, CA 94305 USA

来源：

IEEE DESIGN & TEST OF COMPUTERS | 2004年 / 21卷 / 06期

关键词：

D O I：

10.1109/MDT.2004.96

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Dynamic self-calibration holds the promise of overcoming conservative worst-case design techniques needed to combat deep-submicron processes and operating variations. This article proposes an on-chip point-to-point interconnect scheme characterized by self, calibration that can operate dynamically to achieve the best energy/performance trade-off.

引用

页码：524 / 535

页数：12

共 47 条

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