VFTLP Characteristics of ESD Protection Diodes in Advanced Bulk FinFET Technology

被引：0
|
作者：
Chen, Shih-Hung [1 ]
Linten, Dimitri [1 ]
Scholz, Mirko [1 ]
Hellings, Geert [1 ]
Boschke, Roman [2 ]
Groeseneken, Guido [2 ]
Thean, Aaron [1 ]
机构：
[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
[2] Katholieke Univ Leuven, B-3000 Leuven, Belgium
来源：
2015 37TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD) | 2015年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Beyond 20nm nodes, bulk FinFET is the mainstream technology; however, new process options can result in significant impacts on intrinsic ESD performance. In this work, we study on vfTLP characteristics of two types of ESD diodes. The corresponding TCAD simulations bring an in-depth understanding on the physical mechanism of these ESD diodes.
引用
收藏
页数：6
相关论文
共 50 条
  • [41] Key parameters of BiMOS ESD protection device for UTBB FDSOI advanced technology
    Athanasiou, S.
    Cristoloveanu, S.
    Galy, P.
    2015 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2015,
  • [42] Technology Scaling of ESD Devices in State of the Art FinFET Technologies
    Kim, Sukjin
    Sithanandam, Radhakrishnan
    Seo, Woojin
    Lee, Mijin
    Cho, Sangyoung
    Park, Juho
    Kwon, Hyukhoon
    Kim, Namho
    Jeon, Chanhee
    2020 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2020,
  • [43] Engineering ESD Robust LDMOS SCR Devices in FinFET Technology
    Lee, Jian-Hsing
    Prabhu, Manjunatha
    Natarajan, Mahadeva Iyer
    IEEE ELECTRON DEVICE LETTERS, 2018, 39 (07) : 1011 - 1013
  • [44] ESD protection Diode with Guard Ring Layout Optimized for Latch-up Immunity Enhancement in FinFET technology
    Huang, Kai-Ping
    Peng, Po-Lin
    Chu, Li-Wei
    Chang, Yi-Feng
    Chang, Tzu-Heng
    Lee, Jam-Wem
    Chen, Kuo-Ji
    Song, Ming-Hsiang
    2019 41ST ANNUAL EOS/ESD SYMPOSIUM (EOS/ESD), 2019,
  • [45] Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodology
    Cilento, T.
    Schenkel, M.
    Yun, C.
    Mishra, R.
    Li, J.
    Chatty, K.
    Gauthier, R.
    MICROELECTRONICS RELIABILITY, 2010, 50 (9-11) : 1367 - 1372
  • [46] ESD protection design for advanced CMOS
    Huang, JB
    Wang, GW
    ADVANCES IN MICROELECTRONIC DEVICE TECHNOLOGY, 2001, 4600 : 123 - 131
  • [47] Advanced CMOS Scaling, And FinFET Technology
    Nowak, E. J.
    SIGE, GE, AND RELATED COMPOUNDS 5: MATERIALS, PROCESSING, AND DEVICES, 2012, 50 (09): : 3 - 16
  • [48] Improved ESD Protection in Advanced FDSOI by Using Hybrid SOI/Bulk Co-integration
    Benoist, Thomas
    Fenouillet-Beranger, Claire
    Guitard, Nicolas
    Huguenin, Jean-Luc
    Monfray, Stephane
    Galy, Philippe
    Buj, Christel
    Andrieu, Francois
    Perreau, Pierre
    Marin-Cudraz, David
    Faynot, Olivier
    Cristoloveanu, Sorin
    Gentil, Pierre
    ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS 2010, 2010,
  • [49] ESD Diodes in a Bulk Si Gate-All-Around Vertically Stacked Horizontal Nanowire Technology
    Chen, S. -H.
    Hellings, G.
    Scholz, M.
    Linten, D.
    Mertens, H.
    Ritzenthaler, R.
    Boschke, R.
    Groeseneken, G.
    Horiguchi, N.
    2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2016,
  • [50] Reliability Characterization on Advanced FinFET Technology
    Choi, Kihyun
    Jeong, Taeyoung
    Kim, Jinju
    Choo, Seungjin
    Kim, Younghan
    Yeo, Myung Soo
    Lee, Miji
    Kim, Jinseok
    Lee, Euncheol
    IITC2021: 2021 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (IITC), 2021,
12345