Efficiency of body biasing in 90 nm CMOS for low power digital circuits

被引：10

作者：

von Arnim, K ^{[1
]}

Borinski, E ^{[1
]}

Seegebrecht, P ^{[1
]}

Fiedler, H ^{[1
]}

Brederlow, R ^{[1
]}

Thewes, R ^{[1
]}

Berthold, J ^{[1
]}

Pacha, C ^{[1
]}

机构：

[1] Infineon Technol, Corp Res, D-81730 Munich, Germany

来源：

ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2004年

关键词：

D O I：

10.1109/ESSCIR.2004.1356646

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an evaluation of body biasing based on measured static and dynamic device performance. The efficiency of body biasing in sub-130 nm CMOS circuits strongly depends on the device type and operating temperature. While forward biasing still provides a significant performance gain in a 90 nm CMOS triple well process, the efficiency of reverse biasing nearly vanishes. The impact of the zero temperature coefficient point on low voltage digital circuit design is investigated.

引用

页码：175 / 178

页数：4

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