Efficiency of body biasing in 90 nm CMOS for low power digital circuits

被引：10

作者：

von Arnim, K ^{[1
]}

Borinski, E ^{[1
]}

Seegebrecht, P ^{[1
]}

Fiedler, H ^{[1
]}

Brederlow, R ^{[1
]}

Thewes, R ^{[1
]}

Berthold, J ^{[1
]}

Pacha, C ^{[1
]}

机构：

[1] Infineon Technol, Corp Res, D-81730 Munich, Germany

来源：

ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2004年

关键词：

D O I：

10.1109/ESSCIR.2004.1356646

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an evaluation of body biasing based on measured static and dynamic device performance. The efficiency of body biasing in sub-130 nm CMOS circuits strongly depends on the device type and operating temperature. While forward biasing still provides a significant performance gain in a 90 nm CMOS triple well process, the efficiency of reverse biasing nearly vanishes. The impact of the zero temperature coefficient point on low voltage digital circuit design is investigated.

引用

页码：175 / 178

页数：4

共 50 条

[1] Efficiency of body biasing in 90-nm CMOS for low-power digitcal circuits
von Arnim, K
Borinski, E
Seegebrecht, P
Fiedler, H
Brederlow, R
Thewes, R
Berthold, J
Pacha, C
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (07) : 1549 - 1556
[2] CMOS adaptive biasing circuits for low-power applications
Cardarilli, GC
Ferri, G
1997 21ST INTERNATIONAL CONFERENCE ON MICROELECTRONICS - PROCEEDINGS, VOLS 1 AND 2, 1997, : 747 - 750
[3] Body Biasing-A Circuit Level Approach to Reduce Leakage in Low Power CMOS Circuits
Niranjan, Vandana
Gupta, Maneesha
JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES, 2011, 6 (1-2): : 89 - 99
[4] A low jitter PLL in a 90 nm CMOS digital process
Yin, Haifeng
Wang, Feng
Liu, Jun
Mao, Zhigang
Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 2008, 29 (08): : 1511 - 1516
[5] Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique
Narendra, S
Tschanz, J
Hofsheier, J
Bloechel, B
Vangal, S
Hoskote, Y
Tang, S
Somasekhar, D
Keshavarzi, A
Erraguntla, V
Dermer, G
Borkar, N
Borkar, S
De, V
2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 : 156 - 157
[6] Dynamic SVL and body bias for low leakage power and high performance in CMOS digital circuits
Deshmukh, Jyoti
Khare, Kavita
INTERNATIONAL JOURNAL OF ELECTRONICS, 2012, 99 (12) : 1717 - 1728
[7] Common Source amplifier with feedback biasing in 90nm CMOS
Singh, Tajeshwar
Saether, Trond
Ytterdal, Trond
PRIME 2006: 2ND CONFERENCE ON PH.D. RESEARCH IN MICROELECTRONIC AND ELECTRONICS, PROCEEDINGS, 2006, : 161 - +
[8] Low-Power Low-Cost Direct Digital Frequency Synthesizer Using 90 nm CMOS Technology
Ellaithy, Dina M.
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2022, 31 (11)
[9] A Back Biasing Voltage Generator for 28nm UTBB-FDSOI RVT CMOS Digital Circuits
Pelicia, Marcos Mauricio
Coimbra, Ricardo Pureza
Zanetta, Pedro Barbosa
2018 INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT 2018), 2018, : 1 - 4
[10] Effects of body biasing on the low frequency noise of MOSFETs from a 130 nm CMOS technology
Marin, M
Deen, MJ
de Murcia, M
Llinares, P
Vildeuil, JC
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2004, 151 (02): : 95 - 101

← 1 2 3 4 5 →