RISC-V Online Tutor

被引:0
|
作者
Morgan, Fearghal [1 ]
Beretta, Arthur [2 ]
Gallivan, Ian [1 ]
Clancy, Joseph [1 ]
Rousseau, Frederic [2 ]
George, Roshan [1 ]
Bako, Laszlo [3 ]
Callaly, Frank [1 ]
机构
[1] Natl Univ Ireland, Galway, Ireland
[2] Univ Grenoble Alpes, TIMA, Grenoble INP, CNRS, Grenoble, France
[3] SAPIENTIA Hungarian Univ Transylvania, Targu Mures, Corunca, Romania
来源
关键词
RISC-V; Online learning; Remote laboratory; FPGA; Prototyping; Assembly language; Tutor; Lesson; Course builder; Training;
D O I
10.1007/978-3-030-82529-4_14
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
This paper presents the RISC-V Online Tutor course which provides structured, self-paced RISC-V architecture and applications training. The course browser transparently interacts with remote RISC-V hardware, implemented on an FPGA array. The course is implemented and supported by the reported vicilogic platform which provides online learning, remote FPGA prototyping and course builder. Lessons control remote hardware input signals, probe all RISC-V processor signals and overlay signal widgets on interactive course diagrams. The strategy provides a visually-rich, interactive learn-by-doing experience. The paper presents the course structure, and examples of the interactive lesson pedagogy. User experience, opinion and analytics are presented for a group of 45 users. Results indicate a high level of user satisfaction, and effective independent learning and achievement. Course availability is timely, with the growing interest in the RISC-V open-source Instruction Set Architecture, the call for training materials by RISC-V International, and the increasing demand for practical online learning systems, particularly during the Covid-19 pandemic.
引用
收藏
页码:131 / 143
页数:13
相关论文
共 50 条
  • [31] Systematic RISC-V based Firmware Design
    Herdt, Vladimir
    Grosse, Daniel
    Drechsler, Rolf
    Gerum, Christoph
    Jung, Alexander
    Benz, Joscha-Joel
    Bringmann, Oliver
    Schwarz, Michael
    Stoffel, Dominik
    Kunz, Wolfgang
    PROCEEDINGS OF THE 2019 FORUM ON SPECIFICATION AND DESIGN LANGUAGES (FDL), 2019,
  • [32] HeapSafe: Securing Unprotected Heaps in RISC-V
    De, Asmit
    Ghosh, Swaroop
    2022 35TH INTERNATIONAL CONFERENCE ON VLSI DESIGN (VLSID 2022) HELD CONCURRENTLY WITH 2022 21ST INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (ES 2022), 2022, : 120 - 125
  • [33] Al Acceleration with RISC-V for Edge Computing
    Yang, Chia-Hsiang
    2020 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2020,
  • [34] The Rise of RISC-V from Edge to Cloud
    Su, Charlie Hong-Men
    2020 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2020,
  • [35] Digital Signal Processing Accelerator for RISC-V
    Calicchia, L.
    Ciotoli, V.
    Cardarilli, G. C.
    Di Nunzio, L.
    Fazzolari, R.
    Nannarelli, A.
    Re, M.
    2019 26TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2019, : 703 - 706
  • [36] Survey on RISC-V System Architecture Research
    Liu C.
    Wu Y.-J.
    Wu J.-Z.
    Zhao C.
    Ruan Jian Xue Bao/Journal of Software, 2021, 32 (12): : 3992 - 4024
  • [37] Basic Math Library Implementation for RISC-V
    Li F.
    Guo S.-Z.
    Hao J.-W.
    Hou M.
    Song G.-H.
    Xu J.-C.
    Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2024, 52 (05): : 1633 - 1647
  • [38] Exploring RISC-V Based DNN Accelerators
    Liu, Qiankun
    Amiri, Sam
    Ost, Luciano
    2024 IEEE INTERNATIONAL CONFERENCE ON OMNI-LAYER INTELLIGENT SYSTEMS, COINS 2024, 2024, : 30 - 34
  • [39] A Survey on Thwarting Memory Corruption in RISC-V
    Brohet, Marco
    Regazzoni, Francesco
    ACM COMPUTING SURVEYS, 2024, 56 (02)
  • [40] RISC-V Benchmarking for Onboard Sensor Processing
    Cannizzaro, Michael J.
    Gretok, Evan W.
    George, Alan D.
    2021 IEEE SPACE COMPUTING CONFERENCE (SCC), 2021, : 46 - 59