A hetero-dielectric stack gate SOI-TFET with back gate and its application as a digital inverter

被引：42
|
作者：
Mitra, Suman Kr. [1 ]
Goswami, Rupam [1 ]
Bhowmick, Brinda [1 ]
机构：
[1] Natl Inst Technol Silchar, Dept Elect & Commun Engn, Silchar 788010, Assam, India
来源：
SUPERLATTICES AND MICROSTRUCTURES | 2016年 / 92卷
关键词：
SOI TFET; Hetero-dielectric; Stack gate; C-TFET inverter; FIELD-EFFECT TRANSISTOR; TUNNEL FET; SILICON; MODEL; BODY;
D O I：
10.1016/j.spmi.2016.01.040
中图分类号：
O469 [凝聚态物理学];
学科分类号：
070205 ;
摘要：
A Silicon based two dimensional (2D) hetero-dielectric stack gate SOI Tunneling Field Effect Transistor (SOI-TFET) with back-gate is proposed. Simulation results show that the proposed structure can be scaled down without affecting Subthreshold Swing unlike conventional TFETs with SiO2 as gate dielectric. On state of the device is independent of back-gate voltage unlike MOSFETs. The effects of gate lengths, lengths of high-k dielectric in lower stack (L) and back-gate voltages on the threshold voltage, I-on/I-off and Subthreshold Swing (SS) of the SOI-TFET are analyzed. Capacitance components C-GG, C-GD, C-GS are also observed and device shows good performance as an inverter. The fall time, overshoot and undershoot are not above 27 fs, 1.712% and 0.77% respectively considering mixed mode device and circuit simulation of capacitive loaded inverter. (C) 2016 Elsevier Ltd. All rights reserved.
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页码：37 / 51
页数：15
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