A Parallel Algorithm Based On OpenMP plus STM for FPGA Timing-Driven Placement

被引：0

作者：

Zhang, Jia-qi ^{[1
]}

Lv, Hui-juan ^{[1
]}

Tan, Li-bo ^{[1
]}

Pan, Tao-tao ^{[1
]}

机构：

[1] Natl Digital Switching Syst Engn & Technol Res Ct, Zhengzhou, Henan, Peoples R China

来源：

COMPUTER SCIENCE AND TECHNOLOGY (CST2016) | 2017年

基金：

中国国家自然科学基金;

关键词：

Parallel; OpenMP; Transactional memory; FPGA; Timing-driven placement;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Traditional FPGA placement algorithms based on simulated annealing is time-consuming and thus we have proposed a parallel FPGA timing-driven placement algorithm using OpenMP + STM programming method. In this paper, we distribute swaps to multithreads by OpenMP and protect the shared memory using software transactional memory. An improved timing optimization algorithm is also added in the transaction. Experimental results on MCNC benchmarks demonstrate that our algorithm achieves a speedup of 1.6x and scales well with the increasing of threads. It also reduces the critical path delay by an average of 4.2%.

引用

页码：1185 / 1193

页数：9

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