A ReRAM Memory Compiler with Layout-Precise Performance Evaluation

This paper presents, for the first time, a design automation methodology to generate 1T-1R based Resistive Random Access Memory (ReRAM) arrays with layout-precise performance evaluation. A ReRAM memory compiler is developed and demonstrated on this basis with the ability to account for the unique peripheral circuits devoted to improving performance of ReRAM devices. Given target specifications (e.g. memory capacity, operating frequency), the compiler generates ReRAM sub-arrays and constructs area/power-optimized arrays with performance/power models for evaluation and design space exploration (DSE). The tool is demonstrated with ReRAM device models and 65nm CMOS technology.