Low cost and low power open-loop frequency synthesiser

被引：3

作者：

Haddad, F. ^{[1
]}

Zaid, L. ^{[1
]}

Sangiovanni, A. ^{[1
]}

Scali, R. ^{[2
]}

机构：

[1] Univ Aix Marseille 1, Integrated Circuits Design Team, Inst Mat Microelect & Nanosci Provence, F-13397 Marseille 20, France

[2] Telecom SudParis, F-91011 Evry, France

来源：

ELECTRONICS LETTERS | 2010年 / 46卷 / 14期

关键词：

TRANSCEIVER;

D O I：

10.1049/el.2010.0639

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fully integrated frequency synthesiser based on a low-cost and low-power multifunctional phase-locked loop (PLL) is proposed for frequency shift keying applications. The optimised open-loop modulation circuit and its digital control module are detailed. The 0.166 mm(2) synthesiser is implemented in a 0.28 mu m CMOS technology with 2.5 V supply voltage. Measurement results related to the open-loop frequency drift and demodulated signal together with the PLL lock time are presented.

引用

页码：982 / 983

页数：2

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