A Case for Low-Latency Network-on-Chip using Compression Routers

被引：3

作者：

Niwa, Naoya ^{[1
]}

Shikama, Yoshiya ^{[1
]}

Amano, Hideharu ^{[1
]}

Koibuchi, Michihiro ^{[2
]}

机构：

[1] Keio Univ, Yokohama, Kanagawa, Japan

[2] Natl Inst Informat, Chiyoda Ku, Tokyo, Japan

来源：

2021 29TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED AND NETWORK-BASED PROCESSING (PDP 2021) | 2021年

关键词：

D O I：

10.1109/PDP52278.2021.00029

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The communication talents is a primary concern for designing Network-on-Chips (NoCs) since it significantly affects the parallel application performance on a many-core computer system. To reduce the communication latency, we propose all on-chip router that (de)compresses the contents of an incoming packet before completing switch arbitration. The compression router thus has no latency penalty for the compression operation, whereas it shortens a packet length that decreases the network injection-and-ejection lateney. Evaluation results show that the compression router improves 7.7% of the parallel application performance (IS, CG, FT, and TSPI and 49% of the effective network throughput by 1.8 compression ratio on NoC. The drawback is that the router area and its energy consumption per bit increase by 0.12mm(2) and 1.4 times compared to the conventional virtual-channel router.

引用

页码：134 / 142

页数：9

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