Charging induced missing pattern on metal layers in 65nm technology node

Charging induced Cu trench depletion during via wet clean process has been investigated. Cu missing pattern on metal layers occur predominately at area, which contains via bars or dense vias sitting on wide metal, 2-3x design rule. Comparison was made between different pH solution with pH = 7 and pH = 3.1, with different number of rinse, dry steps. From this study, it was found that regardless of the clean chemistries, Cu depletion occurred predominantly with higher number of rinse and dry steps. The mechanism of charging induced Cu trench depletion can briefly explain as follow. The presence of hillock defect at the via bottom will cause via punch-through. During the cleaning process, oxygen atoms from the cleaning solution can access the punch-through area and react with Cu in the trench to form Cu-O bonds. Of particular interest is that increasing the number of spinning of deionized water (DI) during rinse and dry steps will induce considerable charge build-up on the wafer surface. As a result, a potential is built up across the trench and via layers and induced current flow from trench to via direction, which subsequently resulted in the Cu trench depletion. Thus, with the least number of DI spinning during cleaning process was proven to be an effective way to prevent the charge buildup.