SPA plasma for sub-100nm

被引：0
|
作者：
Murakawa, S
Nemoto, T
Iizuka, V
Yamamoto, N
Ozaki, S
机构：
[1] Tokyo Electron Ltd, Single Wafer Deposit BU, TBS Broadcast Ctr, Minato Ku, Tokyo 1078481, Japan
[2] Tokyo Electron Ltd, Kansai Technol Ctr, Tokyo 1078481, Japan
来源：
SOLID STATE TECHNOLOGY | 2003年 / 46卷 / 01期
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
As semiconductor designs are downscaled to sub-100nm nodes, low thermal budgets and critical requirements for microscopic uniformities, such as low micro-roughness, along with process-dependency on crystal orientation and materials, will all be more important. To address these issues, radical process changes will be needed.
引用
收藏
页码：59 / +
页数：3
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