A 600 MSPS 8-bit folding ADC in 0.18μm CMOS

被引：8

作者：

Wang, ZY ^{[1
]}

Pan, H ^{[1
]}

Chang, CM ^{[1
]}

Yu, HR ^{[1
]}

Chang, MF ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90024 USA

来源：

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

A/D converter; distributed track-and-holds; capacitive averaging; folding and interpolation;

D O I：

10.1109/VLSIC.2004.1346638

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An 8-bit folding A/D converter (ADC) achieves signal-to-noise plus distortion ratio (SNDR) of 40 dB at 600 MSample/s (MSPS) for input signals up to 200 MHz in standard 0.18-mum CMOs. Distributed T/Hs at outputs of the first-stage pre-amplifiers are employed instead of a dedicated front-end T/H. Lateral capacitors are inserted between adjacent T/H outputs to average the random mismatches in charge injection and clock skew among the distributed T/Hs. The ADC consumes 0.5-mm(2) effective chip area and dissipates 207mW from a 1.8V supply.

引用

页码：424 / 427

页数：4

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