Fixed-width multiplier for DSP application

被引：32
|
作者：
Jou, SJ [1 ]
Wang, HH [1 ]
机构：
[1] Natl Cent Univ, Dept Elect Engn, Chungli, Taiwan
来源：
2000 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS | 2000年
关键词：
D O I：
10.1109/ICCD.2000.878302
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A new compensation method that reduce the error of fixed-width multiplier for digital signal processing (DSP) application is proposed. The designs of using this input number based compensation method are carried out on array multiplier and Booth multiplier. The hardware complexity is reduced to about 50% of the original multiplier. Design results show that the new architectures have lower hardware overhead, lower error and fast operation speed as compared with other proposed architectures.
引用
收藏
页码：318 / 322
页数：5
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