CLOCKED SEMI-FLOATING-GATE PSEUDO DIFFERENTIAL PAIR FOR LOW-VOLTAGE ANALOG DESIGN

被引：0
|
作者：
Berg, Y. [1 ]
Mirmotahari, O. [1 ]
机构：
[1] Univ Oslo, Dept Informat, N-0316 Oslo, Norway
来源：
2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2 | 2009年
关键词：
CIRCUITS;
D O I：
10.1109/ECCTD.2009.5275021
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper we present an ultra low-voltage pseudo differential pair based on a clocked semi floating-gate transistor. The clocked semi floating-gate transistors are exploited to increase the current level for ultra low supply voltages and may be used in ultra low voltage mixed signal design. The pseudo differential pair may operate at supply voltages down to 250mV. Simulated data for 90nm CMOS process with a transistor threshold voltage equal to 250mV is included.
引用
收藏
页码：441 / 444
页数：4
相关论文
共 50 条
  • [1] CLOCKED SEMI-FLOATING-GATE ULTRA LOW-VOLTAGE CURRENT MULTIPLIER
    Berg, Y.
    Mirmotahari, O.
    2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2, 2009, : 445 - 448
  • [2] CLOCKED SEMI-FLOATING-GATE ULTRA LOW-VOLTAGE INVERTING CURRENT MIRROR
    Berg, Y.
    Mirmotahari, O.
    IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2009, : 307 - 310
  • [3] CLOCKED SEMI-FLOATING-GATE ULTRA LOW-VOLTAGE SYMMETRIC AND BIDIRECTIONAL CURRENT MIRROR
    Berg, Y.
    Mirmotahari, O.
    IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2009, : 315 - 318
  • [4] Ultra low-voltage bidirectional current mirror using clocked semi-floating-gate transistors
    Berg, Yngvar
    PROCEEDINGS OF THE 13TH IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2010, : 93 - 98
  • [5] A folded floating-gate differential pair for low-voltage applications
    Minch, BA
    ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL IV: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 253 - 256
  • [6] Design and Characterization of Semi-Floating-Gate Synaptic Transistor
    Cho, Yongbeom
    Lee, Jae Yoon
    Yu, Eunseon
    Han, Jae-Hee
    Baek, Myung-Hyun
    Cho, Seongjae
    Park, Byung-Gook
    MICROMACHINES, 2019, 10 (01)
  • [7] An Ultra-Low-Voltage, Semi-Floating-Gate, Domino, Dual-Rail, NOR Gate
    Dadashi, Ali
    Mirmotahari, Omid
    Berg, Yngvar
    2015 IEEE CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS), 2015, : 61 - 64
  • [8] Low-voltage pseudo floating-gate reconfigurable linear threshold elements
    Næss, O
    Aunet, S
    Berg, Y
    Proceedings of the International Joint Conference on Neural Networks (IJCNN), Vols 1-5, 2005, : 675 - 680
  • [9] Comparison of quasi-/pseudo-floating gate techniques and low-voltage applications
    Seo, I
    Fox, RM
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2006, 47 (02) : 183 - 192
  • [10] Comparison of Quasi-/Pseudo-Floating Gate Techniques and Low-Voltage Applications
    Inchang Seo
    Robert M. Fox
    Analog Integrated Circuits and Signal Processing, 2006, 47 : 183 - 192
12345