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- [42] Wafer-level flip chip packages using preapplied anisotropic conductive films (ACFs) IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, 2007, 30 (03): : 221 - 227
- [43] A Flexible Interconnect Technology Demonstrated on a Wafer-Level Chip Scale Package 2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2015, : 859 - 864
- [44] Wafer-level chip scale packaging: Benefits for integrated passive devices IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2000, 23 (02): : 247 - 251
- [45] Drop Failure Modes of A Wafer-Level Chip-Scale Packaging 2013 14TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2013, : 1094 - +
- [46] Wafer-level Optical Packaging for Chip-scale Atomic Magnetometers 2015 16TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, 2015,
- [47] Root cause mechanism for delamination/cracking in stacked die chip scale packages ISSM 2006 CONFERENCE PROCEEDINGS- 13TH INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, 2006, : 219 - 222
- [48] 2-die Wafer-level Chip Scale Packaging enables the smallest TCXO for Mobile and Wearable Applications 2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2015, : 1338 - 1342
- [49] Reliability Challenges and Design Considerations for Wafer-Level Packages 2008 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING, VOLS 1 AND 2, 2008, : 931 - 936