Investigation of asymmetric high-k underlap spacer (AHUS) hybrid FinFET from temperature perspective

This paper estimates the novelty aspects of asymmetric high-k underlap spacer (AHUS) hybrid FinFET devices over conventional FinFET. The AHUS hybrid FinFET combines three advanced technologies i.e., ultra-thin-body (UTB), FinFET and asymmetric high-k spacer on a single silicon on insulator (SOI) platform. This architecture as compared to conventional FinFET further enables the enhancement in device performances without increasing the chip area. Recently, high-k dielectric spacer materials are of research interest due to their better electrostatic control and more immune towards short channel effects (SCEs) in nanoscale devices. This work introduces an asymmetric single layer high-k dielectric spacer in the underlap regions of a hybrid FinFET and claims an effective improvement in low bias applications. We also evaluate the sensitivity of the performance metrics towards temperature (T) variation ranging from 200 to 350 K for the AHUS hybrid FinFET. This further validates the temperature dependency of the proposed device and its application opportunities comprise in modeling analog/RF circuits for a wide range of temperature applications.