A high-speed low-power SAR ADC in 40nm CMOS with combined energy-efficient techniques

被引：5

作者：

Huang, Yujia ^{[1
]}

Meng, Qiao ^{[1
]}

Li, Fei ^{[1
]}

Wu, Jie ^{[1
]}

机构：

[1] Southeast Univ, Inst RF & OE ICs, Nanjing 210096, Jiangsu, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2021年 / 18卷 / 11期

基金：

中国国家自然科学基金;

关键词：

SAR ADC; low-power; dynamic comparator; PIPELINED ADC; SNDR;

D O I：

10.1587/elex.18.20210156

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a high-speed low-power SAR ADC is designed. In this prototype, an improved switching scheme combined with the optimized attenuation capacitor architecture is proposed, showing more power efficiency and is more suitable for high-speed data converters. Meanwhile, an improved synchronous timing strategy is employed, achieving flexible time allocation of DAC settling and comparison in each bit-cycle. In addition, a two-stage non-tail-current-source and single-phase-clock comparator is proposed with more power-efficiency and compatible resolving time. The prototype ADC is fabricated in a 40nm CMOS technology and occupies an active area of 0.04mm(2). An SNDR of 57.18dB and an SFDR of 75.29dB are achieved with the Nyquist rate input at a sampling rate of 160MS/s, consuming 1.3mW at 1.1V supply voltage.

引用

页数：6

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