System-level power analysis methodology applied to the AMBA AHB bus

被引：0

作者：

Caldari, M ^{[1
]}

Conti, M ^{[1
]}

Coppola, M ^{[1
]}

Crippa, P ^{[1
]}

Orcioni, S ^{[1
]}

Pieralisi, L ^{[1
]}

Turchetti, C ^{[1
]}

机构：

[1] Univ Ancona, I-60131 Ancona, Italy

来源：

DESIGNERS FORUM: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION | 2003年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The specification on power consumption of a digital system is extremely important due to the growing relevance of the market of portable devices and must be taken into account since the early phases of a complex System-on-Chip design. In this paper some guidelines are provided for the integration of the information on power consumption in the executable model of parameterized cores, with particular attention to the AMBA AHB bus. This will give important information for the analysis and choice between different design architectures driven by functional, timing and power constraints of the System-on-Chip.

引用

页码：32 / 37

页数：6

共 50 条

[31] HyperspaceFlow: A System-Level Design Methodology for Smart Space
Zeng, Jing
Yang, Laurence T.
Ma, Jianhua
Guo, Minyi
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, 2016, 4 (04) : 568 - 583
[32] A traffic injection methodology with support for system-level synchronization
Informatics and Mathematical Modelling, Technical University of Denmark, Richard Petersens Plads, Lyngby
2800, Denmark
不详
40136, Italy
IFIP Advances in Information and Communication Technology, 2007, (145-161)
[33] A methodology for system-level analog design space exploration
De Bernardinis, F
Vincentelli, AS
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 676 - 677
[34] A system-level design methodology for reconfigurable computing applications
El-Araby, E
El-Ghazawi, T
Gaj, K
FPT 05: 2005 IEEE International Conference on Field Programmable Technology, Proceedings, 2005, : 311 - 312
[35] A traffic injection methodology with support for system-level synchronization
Mahadevan, Shankar
Angiolini, Federico
Sparso, Jens
Benini, Luca
Madsen, Jan
VLSI-SOC: FROM SYSTEMS TO SILICON, 2007, 240 : 145 - +
[36] Capacitor Modeling Methodology for System-level ESD Simulation
Li Xiang
Xie Xiaofei
Xia Nan
Gu Zhengdong
2019 IEEE 26TH INTERNATIONAL SYMPOSIUM ON PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2019,
[37] System-level verification methodology for advanced switch fabrics
Sosa, J
Montiel-Nelson, JA
Navarro, H
Shahdadpuri, M
Sarmiento, R
VLSI CIRCUITS AND SYSTEMS, 2003, 5117 : 187 - 198
[38] Formal refinement checking in a system-level design methodology
Talpin, JP
Le Guernic, P
Shukla, SK
Doucet, F
Gupta, R
FUNDAMENTA INFORMATICAE, 2004, 62 (02) : 243 - 273
[39] System-level Max Power (SYMPO) - A Systematic Approach for Escalating System-level Power Consumption using Synthetic Benchmarks
Ganesan, Karthik
Jo, Jungho
Bircher, W. Lloyd
Kaseridis, Dimitris
Yu, Zhibin
John, Lizy K.
PACT 2010: PROCEEDINGS OF THE NINETEENTH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, 2010, : 19 - 28
[40] System Model Optimization through Functional Models Execution: Methodology and Application to System-level Analysis
Becherini, Francesco
Cencetti, Michele
Pasquinelli, Mauro
2012 IEEE 21ST INTERNATIONAL WORKSHOP ON ENABLING TECHNOLOGIES: INFRASTRUCTURE FOR COLLABORATIVE ENTERPRISES (WETICE), 2012, : 292 - 297

← 1 2 3 4 5 →