The least upper bound of power dissipation in CMOS circuits

被引：0

作者：

Zhao, ZX ^{[1
]}

Min, YH ^{[1
]}

机构：

[1] Chinese Acad Sci, Inst Comp Technol, CAD Lab, Ctr Fault Tolerant Comp, Beijing 100080, Peoples R China

来源：

FIFTH INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN & COMPUTER GRAPHICS, VOLS 1 AND 2 | 1997年

关键词：

power dissipation; CMOS circuit; Boolean process; IC CAD;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Power dissipation has become as important a consideration as speed and area in IC design, In CMOS circuits, power dissipation mainly depends on switching activities, Boolean process introduced by the authors enables us to find a general expression of number of transitions for any input vector pair. This paper presents an approach to tile calculation of Me beast upper bound of power dissipation in CMOS circuits which is significant for estimation of power dissipation and comparison of designs to reduce power dissipation.

引用

页码：506 / 511

页数：6

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