Gain error correction scheme for multiply-by-two gain amplifier in pipelined ADC

被引：0

作者：

Lee, YP ^{[1
]}

Geiger, RL ^{[1
]}

机构：

[1] Iowa State Univ, Dept Elect & Comp Engn, Ames, IA 50011 USA

来源：

42ND MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2 | 1999年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A simple scheme for correcting the gain error of multiply-by-two gain amplifiers that are used in pipelined ADC's using analog technique is proposed. This scheme only requires a programmable capacitor array, a comparator, and a small amount of low speed digital circuitry, which can be shared between different pipelined stages. The resultant gain of two can have accuracy better than 15 bits for typical common-mode voltage error and amplifier and comparator offset voltages.

引用

页码：190 / 193

页数：4

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