Gain error correction scheme for multiply-by-two gain amplifier in pipelined ADC

被引：0

作者：

Lee, YP ^{[1
]}

Geiger, RL ^{[1
]}

机构：

[1] Iowa State Univ, Dept Elect & Comp Engn, Ames, IA 50011 USA

来源：

42ND MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2 | 1999年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A simple scheme for correcting the gain error of multiply-by-two gain amplifiers that are used in pipelined ADC's using analog technique is proposed. This scheme only requires a programmable capacitor array, a comparator, and a small amount of low speed digital circuitry, which can be shared between different pipelined stages. The resultant gain of two can have accuracy better than 15 bits for typical common-mode voltage error and amplifier and comparator offset voltages.

引用

页码：190 / 193

页数：4

共 50 条

[31] A broadband linear-in-decibel variable gain amplifier with low gain error
Lin, Nan
Fang, Fei
Hong, Zhi-Liang
Fang, Hao
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2013, 76 (01) : 73 - 80
[32] A broadband linear-in-decibel variable gain amplifier with low gain error
Nan Lin
Fei Fang
Zhi-Liang Hong
Hao Fang
Analog Integrated Circuits and Signal Processing, 2013, 76 : 73 - 80
[33] A Current-Feedback Instrumentation Amplifier With a Gain Error Reduction Loop and 0.06% Untrimmed Gain Error
Wu, Rong
Huijsing, Johan H.
Makinwa, Kofi A. A.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (12) : 2794 - 2806
[34] A 13-bit 60MS/s Split Pipelined ADC with Background Gain and Mismatch Error Calibration
Ding, Li
Wu, Wenlan
Sin, Sai-Weng
Seng-Pan, U.
Martins, R. P.
PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2013, : 77 - 80
[35] A pipelined dual-channel switched capacitor programmable gain amplifier
Al-Shyoukh, Mohammad
Teutsch, Alexander
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 4875 - +
[36] Gain-boosted dynamic amplifier for pipelined-SAR ADCs
Zhang, Minglei
Liu, Qiyuan
Fan, Xiaohua
ELECTRONICS LETTERS, 2017, 53 (11) : 709 - 710
[37] A pipelined SAR ADC with gain-stage based on capacitive charge pump
Chen, Kairang
Alvandpour, Atila
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2017, 90 (01) : 43 - 53
[38] A pipelined SAR ADC with gain-stage based on capacitive charge pump
Kairang Chen
Atila Alvandpour
Analog Integrated Circuits and Signal Processing, 2017, 90 : 43 - 53
[39] A Low Gain Error Two-Stage dB-Linear Variable Gain Amplifier in 0.35 μm CMOS Process
Wang, Yongsheng
Li, Xinzhi
Zhang, Zhixin
Lai, Fengchang
2017 IEEE 12TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2017, : 367 - 370
[40] Reduction of the influence of amplifier gain setting errors on the performance of adaptive ADC
Malkiewicz, L.
PHOTONICS APPLICATIONS IN ASTRONOMY, COMMUNICATIONS, INDUSTRY, AND HIGH-ENERGY PHYSICS EXPERIMENTS 2013, 2013, 8903

← 1 2 3 4 5 →