Hardware-Accelerated Index Construction for Semantic Web

In this paper, an optimized data structure for managing triples used in a Semantic Web Database and a hardware engine for index construction are presented. We propose an FPGA-centric design, which we call Hardware-Triplestore. As part of the design, a scalable and parallel architecture for Triplestore construction is introduced. We propose a hybrid data structure consisting of three layers, one for every element of the semantic triple. The data structure is optimized for our hardware-centric design and is stored on an external DDR4-Memory. The Hardware-Triplestore is evaluated separately from the rest of the database system and achieves an insertion rate of 1.24 million triples per second, which is 17 times faster than one of the fastest software Triplestore-RDF-3X-.