Asynchronous ARM processor employing an adaptive pipeline architecture

This paper presented an asynchronous ARM processor employing adaptive pipeline and enhanced control schemes. This adaptive pipeline employed stage-skipping and stage-combining. The stage-skipping removed the redundant stage operations, bubbles. The stage-combining was used to unify the neighboring stage when the next stage is idle. Each stage of our implementation had several different datapaths according to the kind of instruction. The instructions in the same pipeline stage could be executed in parallel when they need different datapaths. The outputs obtained from the different datapaths were merged before the WB stage, by the asynchronous reorder buffer. We designed an ARM processor using a 0.35-mu m CMOS standard cell library. In the simulation results, the processor showed approximately 2.8 times speed improvement than its asynchronous counterpart, AMULET3.