Low-Power Memory Addressing Scheme for Fast Fourier Transform Processors

被引:0
|
作者
Xiao, Xin [1 ]
Oruklu, Erdal [1 ]
Saniie, Jafar [1 ]
机构
[1] IIT, Dept Elect & Comp Engn, Chicago, IL 60616 USA
来源
2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 | 2009年
关键词
D O I
10.1109/MWSCAS.2009.5236008
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, a new memory addressing architecture is proposed for low-power radix-2 FFT implementations. Two optimization schemes are presented for dynamic power reduction. First, a multi-bank memory structure is introduced. Second, twiddle factor access times are significantly reduced with a new addressing sequence. For performance evaluation, FFT kernels with transform sizes ranging from 16 to 512 are implemented in CMOS 0.18 mu technology. The synthesis results and architectural analysis indicate significant switching power reduction with no performance penalty. Power reduction factor grows with the transform size, making this architecture ideal for applications requiring long FFT operations.
引用
收藏
页码:653 / 656
页数:4
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