Compact modeling approaches to multiple die stacked chip scale packages

This paper compares several approaches to create compact models for simple and quick prediction of the thermal performance of stacked-die packages. The first approach is the so-called Compact Conduction Model (CCM) by simplifying the die attach with a planar contact resistance and by lumping the solder balls and vias into simplified blocks. The second approach is to further simplify the CCM by lumping the stack dice into a single die with the power dissipation from each die superimposed into one die. The third approach is the so-called two-resistor (2R) compact model that consists of a junction-to-top resistance (thetajc) and a junction-to-board resistance (thetajb). These compact models are compared to the detailed model under different boundary condition scenarios: still air enclosure (JESD51-2), ring cold plate test (JESD51-8), and top cold plate test. The modeling result indicates the compact model can reasonably predict the thermal performance when compared to the detailed model in most boundary conditions. The lumped package substrate layer and the superimposition of multiple dice into an equivalent die can significantly simplify the model, reducing the computer memory and simulation time without scarifying modeling accuracy. Since different levels of errors are associated with different modeling approaches in different boundary conditions, further examination of the possible numerical error in each model approach and further thermal measurements using the actual packages with thermal test dice are needed for thermal model validation.