Fully/partially suspended gate SiC-based FET for power applications

被引：0
|
作者：
Nayak, Suvendu [1 ]
Lodha, Saurabh [1 ]
Ganguly, Swaroop [1 ]
机构：
[1] Indian Inst Technol, Elect Engn Dept, Mumbai 400076, Maharashtra, India
来源：
2021 IEEE LATIN AMERICA ELECTRON DEVICES CONFERENCE (LAEDC) | 2021年
关键词：
NEMFET; Interface; Traps; Suspended; SiC; MOSFETS; DESIGN;
D O I：
10.1109/LAEDC51812.2021.9437932
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A fully/partially suspended gate can overcome the issue of low channel mobility due to interface traps at the Silicon Carbide (SiC) and Silicon Dioxide (SiO 2) interface of a SiC-based DMOS. TCAD simulations (with a deck calibrated to experimental data for SiC) confirms that a suspended gate structure with Air or hybrid dielectrics (stack of Air and SiO 2) provides substantial performance enhancement. The device design (Dielectric spacing) is optimized via simulations. With experimentally reported densities of interface traps the output current indicate that they have a negligible effect on the device performance.
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页数：4
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