An efficient architecture for JPEG2000 coprocessor

被引:9
|
作者
Wu, BF [1 ]
Lin, CF [1 ]
机构
[1] Natl Chiao Tung Univ, Elect & Control Engn Dept, Hsinchu, Taiwan
关键词
JPEG2000; DWT; EBCOT; code block; quad code block;
D O I
10.1109/TCE.2004.1362517
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
JPEG2000 is a new international standard for still image compression. It provides various functions in one single coding stream and the better compression quality than the traditional JPEG, especially in the high compression ratio. However, the heavy computation and large internal memory requirement still restrict the consumer electronics applications. In this paper, we propose a QCB (quad code block)-based DWT method to achieve the higher parallelism than the traditional DWT approach of JPEG2000 coding process. Based on the QCB-based DWT engine, three code blocks con be completely generated after every fixed time slice recursively. Thus, the DWT and EBCOT processors can process simultaneously and the high computational EBCOT then has the higher parallelism of the JPEG2000 encoding system. By changing the output timing of the DWT process and parallelizing with EBCOT, the internal tile memory size can be reduced by a factor of 4. The memory access cycles between the internal tile memory and the code block memory also decrease with the smooth encoding flow(1).
引用
收藏
页码:1183 / 1189
页数:7
相关论文
共 50 条
  • [21] On Efficient Transparent JPEG2000 Encryption
    Stuetz, Thomas
    Uhl, Andreas
    MM&SEC'07: PROCEEDINGS OF THE MULTIMEDIA & SECURITY WORKSHOP 2007, 2007, : 97 - 108
  • [22] Design framework for JPEG2000 system architecture
    Tsutsui, Hiroshi
    Masuzaki, Takahiko
    Hayashi, Yoshiteru
    Taki, Yoshitaka
    Izumi, Tomonori
    Onoye, Takao
    Nakamura, Yukihiro
    INTELLIGENT AUTOMATION AND SOFT COMPUTING, 2006, 12 (03): : 331 - 343
  • [23] Novel architecture for the JPEG2000 block coder
    Freeman, D
    Knowles, G
    JOURNAL OF ELECTRONIC IMAGING, 2004, 13 (04) : 897 - 906
  • [24] Architecture design and VLSI implementation for JPEG2000
    Tsai, TH
    Pan, YN
    Tsai, LT
    PROCEEDINGS OF THE 46TH IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS & SYSTEMS, VOLS 1-3, 2003, : 606 - 609
  • [25] An novel FDWT and IDWT architecture for JPEG2000
    Zhu, K
    Wang, F
    Zhou, XF
    Zhang, QL
    2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 1641 - 1644
  • [26] A Reconfigurable Architecture for DWT and IDWT in JPEG2000
    Hong Qi
    Wang Kanwen
    Cao Wei
    Tong Jiarong
    2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, : 191 - 194
  • [27] A VLSI architecture of EBCOT encoder for JPEG2000
    Liu, LB
    Li, DJ
    Zhang, L
    Wang, ZH
    Chen, HY
    2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 882 - 885
  • [28] VLSI Architecture for MQ coder in JPEG2000
    Ramulu, G.
    Kumar, A. T. Rajesh
    Rao, A. Sarveswara
    Chandra, S. Sharath
    Gopal, M. Madana
    2012 ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN MICROELECTRONICS & ELECTRONICS (PRIMEASIA), 2012, : 106 - 110
  • [29] A high-performance JPEG2000 architecture
    Andra, K
    Chakrabarti, C
    Acharya, T
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2003, 13 (03) : 209 - 218
  • [30] Efficient pass-pipelined VLSI architecture for context modeling of JPEG2000
    Mathiang, Khomkris
    Chitsobhuk, Orachat
    2007 ASIA-PACIFIC CONFERENCE ON COMMUNICATIONS, 2007, : 63 - 66