A Self-Aligning Flip-Chip Assembly Method Using Sacrificial Positive Self-Alignment Structures

被引：9

作者：

Yang, Hyung Suk ^{[1
]}

Zhang, Chaoqi ^{[1
]}

Bakir, Muhannad S. ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

来源：

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | 2016年 / 6卷 / 03期

关键词：

Flip chip; interconnections; microsystems packaging;

D O I：

10.1109/TCPMT.2015.2467318

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A self-aligning flip-chip assembly method is described. The method is capable of correcting up to 150 mu m (five times the radius of solder balls used) of initial misalignment during flip-chip assembly. Critical components of the self-alignment are four polymeric positive self-alignment structures (PSASs), which are fabricated on a substrate, and four inverted pyramid pits, which are etched on a silicon chip in corresponding positions. The PSAS is removed using solvent after the assembly. Resistance of the solder joints is measured to be below 9 m Omega

引用

页码：471 / 477

页数：7

共 50 条

[31] Self-alignment method for solution-processable dielectric structures via joule heating
Janka, M.
Tuukkanen, S.
Joutsenoja, T.
Lupo, D.
THIN SOLID FILMS, 2011, 519 (19) : 6587 - 6590
[32] Adaptive Phototaxis of a Swarm of Mobile Robots using Positive and Negative Feedback Self-Alignment
Mirhosseini, Yoones
Ben Zion, Matan Yah
Dauchot, Olivier
Bredeche, Nicolas
PROCEEDINGS OF THE 2022 GENETIC AND EVOLUTIONARY COMPUTATION CONFERENCE (GECCO'22), 2022, : 104 - 112
[33] Fabrication method of double-microlens Array using self-alignment technology
Kitamura, Kazuya
Okada, Kuniaki
Fujita, Noboru
Nagasaka, Yukiko
Ueda, Minoru
Sekimoto, Yoshihiro
Kurata, Yukio
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2004, 43 (8 B): : 5840 - 5844
[34] Fabrication method of double-microlens array using self-alignment technology
Kitamura, K
Okada, K
Fujita, N
Nagasaka, Y
Ueda, M
Sekimoto, Y
Kurata, Y
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2004, 43 (8B): : 5840 - 5844
[35] Flip-chip solder bumps defect detection using a self-search lightweight framework
Sun, Yu
Su, Lei
Gu, Jiefei
Zhao, Xinwei
Li, Ke
Pecht, Michael
ADVANCED ENGINEERING INFORMATICS, 2024, 60
[36] METHOD TO ACHIEVE CMOS ROX ISOLATION USING LIFT-OFF FOR SELF-ALIGNING IMPLANTED AREAS.
Anon
IBM technical disclosure bulletin, 1986, 28 (11): : 4961 - 4964
[37] Optical module with MU connector interface using self-alignment technique by solder-bump chip bonding
Hayashi, T
Tsunetsugu, H
46TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1996 PROCEEDINGS, 1996, : 13 - 19
[38] Optical module with MU connector interface using self-alignment technique by solder-bump chip bonding
Hayashi, Tsuyoshi
Tsunetsugu, Hideki
Proceedings - Electronic Components and Technology Conference, 1996, : 13 - 19
[39] Accuracy Enhancement of Sub-mm Chip Self-Alignment Using Liquid Surface Tension for Hybrid Integration
Kikuta, Shinya
Hoshino, Satohiko
Yamanishi, Yoshiki
Fukushima, Takafumi
Lee, Kangwook
Koyanagi, Mitsumasa
2016 CONFERENCE ON LASERS AND ELECTRO-OPTICS (CLEO), 2016,
[40] Rapid Initial Self-Alignment Method Using CMKF for SINS Under Marine Mooring Conditions
Pei, Fujun
Yin, Shunan
Yang, Su
IEEE SENSORS JOURNAL, 2021, 21 (08) : 9969 - 9982

← 1 2 3 4 5 →