Low-Power Double-Gate ZnO TFT Active Rectifier

被引:10
|
作者
Sun, Kaige G. [1 ]
Choi, Kyusun [2 ]
Jackson, Thomas N. [1 ]
机构
[1] Penn State Univ, Dept Elect Engn, Ctr Thin Film Devices, Mat Res Inst, University Pk, PA 16802 USA
[2] Penn State Univ, Dept Comp Sci & Engn, University Pk, PA 16802 USA
基金
美国国家科学基金会;
关键词
Active rectifier; thin film transistors; TFT; double gate; plasma-enhanced atomic layer deposition; zinc oxide; ZnO TFTs; oxide TFTs; oxide semiconductor transistors; energy harvesting; ENERGY;
D O I
10.1109/LED.2016.2527832
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This letter reports a low-power full-wave active rectifier using double-gate ZnO thin-film transistors (TFTs). The active rectifier is designed to operate at low voltage and low power to allow integration with mechanical energy harvesters. Double-gate TFTs allow the TFT threshold voltage to be tuned and enable enhancement/depletion-mode circuits with high gain and low power consumption. The active rectifier is designed to work with input voltage as small as 200-mV peak-to-peak and frequencies up to 4 Hz. The active rectifier circuit includes 12 TFTs and operates with a power consumption <150 nW. The low fabrication temperature for the active rectifier circuit allows direct and distributed integration with micro-electromechanical energy harvesters.
引用
收藏
页码:426 / 428
页数:3
相关论文
共 50 条
  • [1] Double-Gate ZnO TFT Active Rectifier
    Sun, Kaige G.
    Choi, Kyusun
    Jackson, Thomas N.
    2014 72ND ANNUAL DEVICE RESEARCH CONFERENCE (DRC), 2014, : 269 - +
  • [2] A low-power reconfigurable logic array based on double-gate transistors
    Beckett, Paul
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2008, 16 (02) : 115 - 123
  • [3] Double-gate SOI devices for low-power and high-performance applications
    Roy, K
    Mahmoodi, H
    Mukhopadhyay, S
    Ananthan, H
    Bansal, A
    Cakici, T
    ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, 2005, : 217 - 224
  • [4] Negative capacitance double-gate MOSFET for advanced low-power electronic applications
    Kumar, Amit
    Communication, Saurabh Chaturvedi
    Kumar, Satyendra
    MICROELECTRONICS JOURNAL, 2025, 159
  • [5] Double-gate SOI devices for low-power and high-performance applications
    Roy, K
    Mahmoodi, H
    Mukhopadhyay, S
    Ananthan, H
    Bansal, A
    Cakici, T
    19TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2005, : 445 - 452
  • [6] On-Current Improvement in Bulk-Accumulated Double-Gate ZnO TFT
    Jaiswal, Saurabh
    Dubey, Divya
    Singh, Shilpi
    Goswami, Rupam
    Goswami, Manish
    Kandpal, Kavindra
    JOURNAL OF ELECTRONIC MATERIALS, 2025, 54 (01) : 51 - 58
  • [7] CHARACTERISTICS OF DOUBLE-GATE a-IGZO TFT
    He, Xin
    Xiao, Xiang
    Deng, Wei
    Wang, Longyan
    Wang, Ling
    Chi, Shipeng
    Shao, Yang
    Chan, Mansun
    Zhang, Shengdong
    2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2014,
  • [8] A low-power, highly scalable, vertical double-gate MOSFET using novel processes
    Cho, Hoon
    Kapur, Pawan
    Kalavade, Pranav
    Saraswat, Krishna C.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (02) : 632 - 639
  • [9] Low-power tunable analog circuit blocks based on nanoscale double-gate MOSFETs
    Kaya, Savas
    Hamed, Hesham F. A.
    Starzyk, Janusz A.
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2007, 54 (07) : 571 - 575
  • [10] Simulation Study of the Slope-Channel Double-Gate MOSFET for Low-Power Applications
    Zhang, Maolin
    Guo, Yufeng
    Chen, Jing
    Zhang, Jun
    Yao, Jiafei
    2019 CROSS STRAIT QUAD-REGIONAL RADIO SCIENCE AND WIRELESS TECHNOLOGY CONFERENCE (CSQRWC), 2019,