Modeling and simulation of a serial-link multistage interconnection network using VHDL

A serial-link multistage interconnection network has been proposed [1] as an alternative for a full-mesh single stage network [2-4] for connecting an array of processors and memory modules. In this network columns of switches are used to connect the serial bi-directional links to the processors and memory elements. The inner column of switches are connected point-to-point where the outer columns are connected in binary tree topology. This paper describes a modeling and simulation study of the performance of the network using VHDL. Since this level of modeling is low level, the results have been compared against a serial point-to-point network described in VHDL. Both networks have been modeled in Network II.5 and the results of response time and link utilization are also included.