Scaling transistors into the deep-submicron regime

The accurate control of dopant profiles in the source, drain, and channel regions in metal oxide semiconductor (MOS) transistors is critical to the continued scaling of the silicon transistor. In the near future, junction depths of less than 10 nm with junction steepnesses better than 2 nm/decade will be required. Current device-fabrication methods have not been able to create these profiles, due to interactions of the dopant atoms with point and extended defects. To continue the scaling trend of the past 30 years, new methods will need to be developed, based on a fundamental understanding of these interactions.