A Run-time Reconfigurable Cache Architecture

Cache parameters for CPU architectures are typically defined for a best overall match regarding the targeted field of applications. However, such may hinder high-performance execution of single applications and also does not account for cache access phases as occurring in long-running applications, e.g. from field of high-performance computing. It has been shown that matching the cache parameters to a running application results in both application speed-up and increased energy efficiency. The aim of the presented work is to create a versatile, reconfigurable cache hardware infrastructure for cache performance analysis. Such an infrastructure enables real-time monitoring of running applications and therefore is able to better trace a running application's behaviour compared to off-line analysis of a more or less reduced trace. In this paper, we will address the problems and side-effects of a run-time reconfigurable cache architecture. to which we present appropriate solutions. We will also give,in outline of the upcoming hardware prototype.