Acceleration techniques for chip-multiprocessor simulator debug

被引：0
|
作者：
Wang, Haixia [1 ]
Wang, Dongsheng [1 ]
Li, Peng [1 ]
机构：
[1] Tsinghua Univ, Natl Lab Informat Sci & Technol, Res Inst Informat Technol, Beijing 100084, Peoples R China
来源：
ADVANCES IN COMPUTER SYSTEMS ARCHITECTURE, PROCEEDINGS | 2006年 / 4186卷
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
By exploring thread-level parallelism, chip multiprocessor (CMP) can dramatically improve the performance of server and commercial applications. However, complex CMP chip architecture made debugging work time-consuming and rather hard. In this paper, based on the experience of debugging CMP simulator ThumpCMP, we present a set of acceleration techniques, including automatic cache-coherence check, fast error location, and workload rerun times reducing technique. The set of techniques have been demonstrated to be able to make CMP chip debugging work much easier and much faster.
引用
收藏
页码：509 / 515
页数：7
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