3D/2.5D Stacked IC Cost Modeling and Test Flow Selection

The industry is preparing itself and putting tremendous effort in place to bring through silicon via (TSV) based 2.5D and 3D-SIC technology closer to market. Such emerging technologies promise major advantages such as increased electrical performance, reduced power consumption due to shortened interconnects, heterogeneous integration, reduced form factor, etc. One of the major challenges that has to be solved before having a successful commercialization of such technologies is overall cost control and optimization. Semiconductor manufacturing is a complex process and consists of many high-precision steps; hence, it is a defect-prone process. Consequently, and as it is the case for any IC, TSV-based 2.5D and 3D-SICs must be tested in order to guarantee the outgoing product quality and reliability. For TSV-based ICs, testing is even more critical as these devices typically contain complex die designs in advanced technology nodes. Moreover, inherent to their manufacturing process, these devices provide several test moments such as pre-bond (before stacking), mid-bond (on a partial stack), post-bond (on a completed stack), and final testing (on a packaged device). This results into a large space of test flows; each with its own cost. The test flow needs to be optimized based on yield and cost parameters of an individual product and that is a complex optimization problem. In addition, different test flows, executed after manufacturing, may require different design-for-test features, which need to be incorporated in the various dies during their early design stages. This talk discusses 2.5 and 3D-SIC cost modelling and presents 3D-COSTAR to optimize test flows of 2.5D and 3D-SICs. 3D-COSTAR uses input parameters that cover the entire 2.5D-/3D-SIC production flow: 1) design; 2) manufacturing; 3) test; 4) packaging; and 5) logistics. It is aware of the stack build-up (2.5D versus 3D, multiple towers; face-to-face or face-to-back) and stacking process (die-to-die, die-to-wafer, or wafer-to-wafer). The tool produces three key analysis parameters: 1) product quality, expressed as defect level (test escape rate) in DPPM (defective parts per million); 2) overall stack cost; and 3) breakdown per cost type. In addition, the talk provides many cases studies analyses and reports about three case studies with respect to 2.5D and 3D-SIC test cost optimization; these are: (a) the impact of the fault coverage of the interposer pre-bond test on the overall cost, (b) whether it is more advantageous to perform pre-bond testing for the active dies using dedicated probe pads or through micro-bumps, and (c) the impact of mid-bond testing and logistics on the overall cost.