A novel queueing architecture for background calibration of pipeline ADCs

A novel queueing architecture for background calibration of pipeline ADCs is presented. By controlling the ADC conversion rate this queue enables dynamic control of the calibration rate and achieves required gain estimates in fewer conversion cycles than previously reported designs. The queue can store any required number of input samples during a calibration cycle without contributing extra noise to the input signal path. The architecture also facilitates calibration of front-end sample and holds (S/Hs) in pipeline ADCs. Operation of the queue is demonstrated with existing background calibration algorithms and dynamic calibration rate control is demonstrated with the use of a 12-stage pipeline model. Existing queue designs are evaluated and compared qualitatively with the proposed architecture.