NanoFS: a hardware-oriented file system

被引:1
|
作者
Ruiz-de-Clavijo, P. [1 ]
Ostua, E. [1 ]
Juan, J. [1 ]
Bellido, M. J. [1 ]
Viejo, J. [1 ]
Guerrero, D. [1 ]
机构
[1] Univ Seville, Dept Tecnol Elect, ETS Ingn Informat, E-41012 Seville, Spain
关键词
embedded systems; formal specification; storage management; programmable device; file system specification; data fetch operation; file lookup; optimal hardware implementation; internal layout; storage-class memory; embedded system; hardware-oriented file system; NanoFS;
D O I
10.1049/el.2013.1961
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
NanoFS is a novel file system for embedded systems and storage-class memories (like flash) and is specially designed to be directly implemented in hardware. NanoFS is based on an original internal layout intended to achieve an optimal hardware implementation of the file system's file lookup and data fetch operations. File system specification on a sample reader module completely implemented in a programmable device is introduced.
引用
收藏
页码:1216 / 1218
页数:2
相关论文
共 50 条
  • [31] A fast hardware-oriented algorithm for cellular mobiles positioning
    Salamah, M
    Doukhnitch, E
    Devrim, D
    COMPUTER AND INFORMATION SCIENCES - ISCIS 2004, PROCEEDINGS, 2004, 3280 : 267 - 277
  • [32] Simple hardware-oriented algorithms for cellular mobiles positioning
    Najiminaini, M.
    Doukhnitch, E.
    Salamah, M.
    2007 IEEE INTERNATIONAL CONFERENCE ON PERVASIVE SERVICES, 2007, : 157 - 160
  • [33] Performance Evaluation of Hardware-Oriented Seam Carving Algorithm
    Kohata, Yasuhide
    Desaki, Yoshihisa
    2014 IEEE 3RD GLOBAL CONFERENCE ON CONSUMER ELECTRONICS (GCCE), 2014, : 315 - 316
  • [34] Hardware-oriented deep reinforcement learning for edge computing
    Yamagishi, Yoshiharu
    Kaneko, Tatsuya
    Akai-Kasaya, Megumi
    Asai, Tetsuya
    IEICE NONLINEAR THEORY AND ITS APPLICATIONS, 2021, 12 (03): : 526 - 544
  • [35] A Hardware-oriented Learning Algorithm for a Digital Spiking Neuron
    Torikai, Hiroyuki
    Hashimoto, Sho
    2008 IEEE INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOLS 1-8, 2008, : 2472 - 2479
  • [36] A flexible hardware-oriented fast algorithm for motion estimation
    Yu, FQ
    Wilson, AN
    1997 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I - V: VOL I: PLENARY, EXPERT SUMMARIES, SPECIAL, AUDIO, UNDERWATER ACOUSTICS, VLSI; VOL II: SPEECH PROCESSING; VOL III: SPEECH PROCESSING, DIGITAL SIGNAL PROCESSING; VOL IV: MULTIDIMENSIONAL SIGNAL PROCESSING, NEURAL NETWORKS - VOL V: STATISTICAL SIGNAL AND ARRAY PROCESSING, APPLICATIONS, 1997, : 2681 - 2683
  • [37] A Hardware-Oriented Dropout Algorithm for Efficient FPGA Implementation
    Yeoh, Yoeng Jye
    Morie, Takashi
    Tamukoh, Hakaru
    NEURAL INFORMATION PROCESSING (ICONIP 2017), PT VI, 2017, 10639 : 821 - 829
  • [38] A Hardware-oriented IME Algorithm and Its Implementation for HEVC
    Ye, Xin
    Ding, Dandan
    Yu, Lu
    2014 IEEE VISUAL COMMUNICATIONS AND IMAGE PROCESSING CONFERENCE, 2014, : 205 - 208
  • [39] HARDWARE-ORIENTED ALGORITHMS FOR THE FAST SYMBOLIC CALCULATION OF THE DFT
    BETH, T
    FUMY, W
    ELECTRONICS LETTERS, 1983, 19 (21) : 901 - 902
  • [40] Hardware-Oriented Dual Stream Object Recognition System using Binarized Neural Networks
    Yoshimoto, Yuma
    Tamukoh, Hakaru
    2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2020,