Investigation of the stepped split protection gate L-Trench SOI LDMOS with ultra-low specific on-resistance by simulation

An ultra-low specific on-resistance SOI LDMOS with stepped split protection gate L-trench (SSG LT LDMOS) is proposed. On the one hand, the stepped split protection gate (PG) not only assists in depleting the drift region but also modulates the vertical electric field. In addition, the PG diminishes the Miller capacitance, which decreasing gate-drain charge (Q(gd)) and switching losses of the proposed structure. On the other hand, the breakdown voltage (BV) of the proposed structure can be enhanced by the introduced L-trench (LT) and siliconon-insulator (SOI) layer. According to the enhanced dielectric layer field (ENDIF) effect, the depletion layer and inversion layer are formed in the both sides of the LT and the SOI layer to increase BV. The LT conspicuously shortens the length of the drift region while the high BV is maintained, which further reduces the specific on- resistance (R-on,R-sp) . The simulation results show that comparing with the conventional structure, R(on,sp )is reduced by 77.2%, the figure of merit (FOM1 = BV2/R-on,R-sp) and BV can be increased by 486.6% and 13.7%, respectively. Meanwhile, The loss figure of merit (FOM2 = R-on,R-sp*Q(gd)) is reduced by 83.8%.