Mobility Enhanced Power CMOS

被引：0

作者：

Jang, Jaejune ^{[1
]}

Jung, Jaehyeon ^{[1
]}

Chang, Hoon ^{[1
]}

Kim, Yongdon ^{[1
]}

Park, Seoin ^{[1
]}

Kim, Hyunju ^{[1
]}

Kim, Jaehwan ^{[1
]}

Yi, Sangbae ^{[1
]}

机构：

[1] Samsung Elect, Youngin City, Gyeonggi Do, South Korea

来源：

2013 25TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper introduces mobility enhanced 5V CMOS through geometry optimization in 130nm technology for state-f-the-art R-SP performance. By realizing < 100 > channel direction on (100) wafer with grid-type layout, mobility of both NMOS and PMOS is enhanced in addition to increased effective width. Furthermore even higher mobility is achieved through introduction of biaxial compressive stress from nearby STI islands. As a result, I-DSAT and I-DLIN increase by 24%/29% for NMOS and 29%/37% for PMOS respectively compared to standard bar-type layout. All of this is obtained without any process change.

引用

页码：155 / 158

页数：4

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