Design of Robust Ultra-Low Power CMOS Voltage Controlled Ring Oscillator with Enhanced Performance

被引:0
|
作者
Walunj, Rupali A. [1 ]
Pable, Sachin D. [2 ]
Kharate, Gajanan K. [3 ]
机构
[1] Matoshri Coll Engn & Res Ctr, Dept Elect & Telecommun, Nasik, Maharashtra, India
[2] Govt Polytech Nasik, Dept Elect & Telecommun, Nasik, Maharashtra, India
[3] Matoshri Coll Engn & Res Ctr, Nasik, Maharashtra, India
关键词
Sub threshold circuit; ultra- low power(ULP); Voltage Controlled Oscillator (VCO); current starved voltage controlled Oscillator(CSVCO); Monte carlo Simulation;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Sub threshold circuits have proven their ability to satisfy the demand of ultra low power consumption of today's battery operated applications. However, the elevated variability and degraded performance issues of sub threshold circuits need to be addressed. This paper focuses on dual knobs of variability and performance of sub threshold CMOS VCO and proposes an ultra low power CMOS voltage controlled ring oscillator with enhanced performance and reduced variability. The proposed DTCSVCO configuration exhibits better performance and slew as compared to conventional CSVCO by almost 37% and 10.87% respectively. Width optimization further improves the performance of proposed DTCSVCO by almost 49% at the cost of increase in PDP of 32%. Process and temperature variability is also investigated and the results illustrates that the proposed DTCSVCO exhibits better robustness compared to conventional CSVCO. The simulation results at different process corner over a wide range of temperature are consistent.
引用
收藏
页码:235 / 239
页数:5
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