Comparison of heavy-ion induced SEU for D-and TMR-flip-flop designs in 65-nm bulk CMOS technology

被引：6

作者：

He YiBai ^{[1
]}

Chen ShuMing ^{[1
,2
]}

机构：

[1] Natl Univ Def Technol, Sch Comp Sci, Changsha 410073, Hunan, Peoples R China

[2] Natl Univ Def Technol, Sci & Technol Parallel & Distributed Proc Lab, Changsha 410073, Hunan, Peoples R China

来源：

SCIENCE CHINA-INFORMATION SCIENCES | 2014年 / 57卷 / 10期

基金：

中国国家自然科学基金;

关键词：

SEU; flip-flop; TMR; heavy-ion; frequency; SINGLE EVENT UPSETS; ERROR RATES; NM; COMBINATORIAL;

D O I：

10.1007/s11432-014-5100-1

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Heavy ion experiments were performed on D flip-flop (DFF) and TMR flip-flop (TMRFF) fabricated in a 65-nm bulk CMOS process. The experiment results show that TMRFF has about 92% decrease in SEU cross-section compared to the standard DFF design in static test mode. In dynamic test mode, TMRFF shows much stronger frequency dependency than the DFF design, which reduces its advantage over DFF at higher operation frequency. At 160 MHz, the TMRFF is only 3.2x harder than the standard DFF. Such small improvement in the SEU performance of the TMR design may warrant reconsideration for its use in hardening design.

引用

页码：1 / 7

页数：7

共 32 条

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