Pre-synthesis Optimization for Asynchronous Circuits Using Compiler Techniques

被引:0
|
作者
ZamanZadeh, Sharareh [1 ]
Najibi, Mehrdad [1 ]
Pedram, Hossein [1 ]
机构
[1] Amirkabir Univ Technol, Tehran, Iran
关键词
Compiler techniques; Optimization; High level synthesis of asynchronous circuits;
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
The effectiveness of traditional compiler techniques employed in high-level synthesis of synchronous circuits aiming to present a generic code is studied for asynchronous synthesis by considering the special features of these circuits. The compiler methods can be used innovatively to improve the synthesis results in both power consumption and area. The compiler methods like speculation, loop invariant code motion and condition expansion are applicable in decreasing mass of handshaking circuits and intermediate modules. Moreover, they eliminate conditional access to variables and ports and reducing the amount of completion detection circuits. The approach is Superimposed on to Persia synthesis toolset as a presynthesis source-to-source transformation phase, and results shows on average 22% improvement in terms of area and 24% in power consumption for asynchronous benchmarks.
引用
收藏
页码:951 / 954
页数:4
相关论文
共 50 条
  • [1] Reimbursing the handshake overhead of asynchronous circuits using compiler pre-synthesis optimizations
    Zamanzadeh, S.
    Mirza-Aghatabar, M.
    Najibi, M.
    Pedram, H.
    Sadeghi, A.
    11TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - ARCHITECTURES, METHODS AND TOOLS : DSD 2008, PROCEEDINGS, 2008, : 290 - +
  • [2] SYNTHESIS FOR TESTABILITY TECHNIQUES FOR ASYNCHRONOUS CIRCUITS
    KEUTZER, K
    LAVAGNO, L
    SANGIOVANNIVINCENTELLI, A
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1995, 14 (12) : 1569 - 1577
  • [3] Automatic optimization techniques for formal verification of asynchronous circuits
    Boubekeur, M.
    Schellekens, M. P.
    2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4, 2007, : 283 - 286
  • [4] COMPILER OPTIMIZATION TECHNIQUES
    INSELBERG, A
    MAZOR, S
    COMPUTER DESIGN, 1981, 20 (11): : 245 - &
  • [5] Maximizing conditional reuse by pre-synthesis transformations
    Peñalba, O
    Mendías, JM
    Hermida, R
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2002 PROCEEDINGS, 2002, : 1097 - 1097
  • [6] Using compiler optimization techniques to detect equivalent mutants
    Offutt, A.Jefferson
    Craft, W.Michael
    Software Testing Verification and Reliability, 1994, 4 (03) : 131 - 154
  • [7] Quasi-Delay-Insensitive Compiler: Automatic Synthesis of Asynchronous Circuits from Verilog Specifications
    Zhou, Rong
    Chong, Kwen-Siong
    Gwee, Bah-Hwee
    Chang, Joseph S.
    2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2011,
  • [8] SYNTHESIS OF ASYNCHRONOUS CIRCUITS
    HATTORI, M
    NOGUCHI, H
    JOURNAL OF THE MATHEMATICAL SOCIETY OF JAPAN, 1966, 18 (04) : 405 - +
  • [9] Pre-synthesis area estimation of reconfigurable streaming accelerators
    Mondal, Somsubhra
    Memik, Seda Ogrenci
    Bellas, Nikolaos
    2006 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, 2006, : 813 - 816
  • [10] Synthesis of asynchronous circuits using early data validity
    Gupta, N
    Edwards, DA
    18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: POWER AWARE DESIGN OF VLSI SYSTEMS, 2005, : 799 - 803