Adaptive pipeline depth control for processor power-management

被引：20

作者：

Efthymiou, A ^{[1
]}

Garside, JD ^{[1
]}

机构：

[1] Univ Manchester, Dept Comp Sci, Manchester M13 9PL, Lancs, England

来源：

ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS | 2002年

关键词：

D O I：

10.1109/ICCD.2002.1106812

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A method of managing the power consumption of an embedded, single-issue processor by controlling its pipeline depth is proposed. The execution time will be increased but, if the method is applied to applications with slack time, the user-perceived performance may not be degraded. Two techniques are shown using an existing asynchronous processor as a starting point. The first method controls the pipeline occupancy using a token mechanism, the second enables adjacent pipeline stages to be merged, by making the latches between them 'permanently' transparent. An energy reduction of up to 16% is measured, using a collection of five benchmarks.

引用

页码：454 / 457

页数：4

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