A 23mW 24GS/s 6b Time-Interleaved Hybrid Two-Step ADC in 28nm CMOS

被引：0
|
作者：
Xu, Benwei [1 ]
Zhou, Yuan [1 ]
Chiu, Yun [1 ]
机构：
[1] Univ Texas Dallas, Richardson, TX 75083 USA
来源：
2016 IEEE SYMPOSIUM ON VLSI CIRCUITS (VLSI-CIRCUITS) | 2016年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We present a power-and area-efficient 24GS/s, 6b, 16-way time-interleaved (TI) ADC array, featuring a voltage-time (v/t) hybrid two-step structure for high-speed and low-power operation, a crosstalk-free SAR DAC topology and a non-hierarchical sampling frontend obviating reference and input buffers, respectively, for power and area savings. Background timing-skew calibration via dithering a reference ADC is also reported. Fabricated in 28nm CMOS, the prototype ADC array consumes 23mW at 24GS/s and measures an SNDR/SFDR of 35/54dB for a low-frequency input and 29/41dB for a Nyquist input, respectively. The core area of the ADC is 0.03mm(2)
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