On the design of low-voltage, low-power CMOS analog multipliers for RF applications

被引：8
|
作者：
Debono, CJ
Maloberti, F
Micallef, J
机构：
[1] Univ Pavia, Dept Elect, I-27100 Pavia, Italy
[2] Univ Malta, Dept Microelectron, Msida, Malta
[3] Univ Pavia, Dept Elect, I-27100 Pavia, Italy
[4] Univ Malta, Dept Microelect, Msida, Malta
来源：
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2002年 / 10卷 / 02期
关键词：
analog multiplier; CMOS RF; low power; low voltage;
D O I：
10.1109/92.994995
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Novel low-voltage, low-power techniques in the design of portable wireless communication systems are required. Two system examples of low-power analog multipliers operating from a 1.2 V supply are presented. These proposed structures achieve the required multiplication function by using current processing. The circuits were fabricated using standard double-poly CMOS processes for a 900 MHz application. Measurement results of the prototypes are comparable to other higher voltage designs.
引用
收藏
页码：168 / 174
页数：7
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