A cellular structure for a versatile Reed-Solomon decoder

被引：13

作者：

Shayan, YR ^{[1
]}

LeNgoc, T ^{[1
]}

机构：

[1] CONCORDIA UNIV,DEPT ELECT & COMP ENGN,MONTREAL,PQ H3G 1M8,CANADA

来源：

IEEE TRANSACTIONS ON COMPUTERS | 1997年 / 46卷 / 01期

关键词：

cellular structure; comparison of RS decoding structures; time domain RS decoder; versatile RS decoder; VLSI;

D O I：

10.1109/12.559805

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new cellular structure for a versatile Reed-Solomon (RS) decoder is introduced based on time domain decoding algorithm. The time domain decoding algorithm is restructured to be suitable for introducing the cellular structure. The main advantages of this structure are its versatility and very simple cellular structure. By versatile decoder we mean a decoder that can be programmed to decode any (n, k) RS code defined in Galois field 2(m) with a fixed block length n and a fixed symbol size m. This decoder can correct both errors and erasures for any message length k. The introduced decoder is cellular and has a very simple structure and hence it is suitable for VLSI designs.

引用

页码：80 / 85

页数：6

共 50 条

[31] An enhanced Reed-Solomon decoder for wireless communication systems
Egorov, S
Markarian, G
1ST INTERNATIONAL SYMPOSIUM ON WIRELESS COMMUNICATION SYSTEMS 2004, PROCEEDINGS, 2004, : 198 - 202
[32] Design of a high-speed Reed-Solomon decoder
Baek, JH
Kang, JY
Sunwoo, MH
2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS, 2002, : 793 - 796
[33] Design of a Novel Serial United Reed-Solomon Decoder
An X.
Liang Y.
Zhang W.
Hsi-An Chiao Tung Ta Hsueh/Journal of Xi'an Jiaotong University, 2021, 55 (03): : 65 - 71
[34] ON THE DECODER ERROR-PROBABILITY FOR REED-SOLOMON CODES
MCELIECE, RJ
SWANSON, L
IEEE TRANSACTIONS ON INFORMATION THEORY, 1986, 32 (05) : 701 - 703
[35] Efficient recursive cell architecture for the Reed-Solomon decoder
Lee, DH
Kim, JT
JOURNAL OF THE KOREAN PHYSICAL SOCIETY, 2002, 40 (01) : 82 - 86
[36] Reed-Solomon encoder & decoder design, simulation and synthesis
Ardalan, S
Raahemifar, K
Yuan, F
Geurkov, V
CCECE 2003: CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-3, PROCEEDINGS: TOWARD A CARING AND HUMANE TECHNOLOGY, 2003, : 255 - 258
[37] A parallel Reed-Solomon decoder on the imagine stream processor
Wen, Mei
Zhang, Chunyuan
Wu, Nan
Li, Haiyan
Li, Li
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2004, 3358 : 28 - 33
[38] A fast parallel Reed-Solomon decoder on a reconfigurable architecture
Koohi, A
Bagherzadeh, N
Pan, CZ
CODES(PLUS)ISSS 2003: FIRST IEEE/ACM/IFIP INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN & SYSTEM SYNTHESIS, 2003, : 59 - 64
[39] An efficient Reed-Solomon decoder VLSI with erasure correction
Oh, K
Sung, WY
SIPS 97 - 1997 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION, 1997, : 193 - 201
[40] An ultra high-speed Reed-Solomon decoder
Lee, H
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 1036 - 1039

← 1 2 3 4 5 →