eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip

被引：0
|
作者：
Beldachi, Arash Farhadi [1 ]
Hollis, Simon [2 ]
Nunez-Yanez, Jose L. [1 ]
机构：
[1] Univ Bristol, Dept Elect Engn, Bristol BS8 1TH, Avon, England
[2] Univ Bristol, Dept Comp Sci, Bristol BS8 1TH, Avon, England
来源：
IET COMPUTERS AND DIGITAL TECHNIQUES | 2014年 / 8卷 / 03期
基金：
英国工程与自然科学研究理事会;
关键词：
field programmable gate arrays; mesh generation; network-on-chip; topology; eXtended Torus routing algorithm for networks-on-chip; inner-torus building blocks; nonregular global topologies; FPGA; XTRANC algorithm; mesh topology; application behaviour; resource availability; PERFORMANCE;
D O I：
10.1049/iet-cdt.2013.0087
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a novel routing algorithm called eXtended Torus routing algorithm for networks-on-chip (XTRANC) which supports topologyies based on a variable number and size of inner-torus building blocks. The inner-tori partition a traditional mesh network into an arbitrary number of sub-networks to increase the mesh performance. The sub-networks can generate non-regular global topologies which are also supported by the XTRANC algorithm. XTRANC is especially suitable for dynamically reconfigurable networks mapped to commercial FPGAs in which additional links are added to the mesh topology at run-time to reduce congestion depending on application behaviour and resource availability. XTRANC allows the insertion of links as requested by different parts of the application without centralized control and this research shows that despite this dynamic behaviour the routing algorithm remains deadlock free.
引用
收藏
页码：148 / 162
页数：15
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