共 50 条
- [1] Small Delay Testing for TSVs in 3-D ICs 2012 49TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2012, : 1031 - 1036
- [2] 3-D ICs with TSVs:The hard work continues Electronic Device Failure Analysis, 2013, 15 (03): : 46 - 47
- [3] Modeling of Coupled TSVs in 3D ICs 2012 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC), 2012, : 7 - 11
- [4] Layer Ordering to Minimize TSVs in Heterogeneous 3-D ICs 2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, : 1926 - 1929
- [6] Interposer Power Distribution Network (PDN) Modeling Using a Segmentation Method for 3-D ICs With TSVs IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2013, 3 (11): : 1891 - 1906
- [7] THERMAL ANALYSIS OF 3D ICS WITH TSVS PLACEMENT OPTIMIZATION PROCEEDINGS OF THE ASME INTERNATIONAL TECHNICAL CONFERENCE AND EXHIBITION ON PACKAGING AND INTEGRATION OF ELECTRONIC AND PHOTONIC MICROSYSTEMS, 2019, 2020,
- [9] Modeling of Power Distribution Network based on Multi-Walled Carbon Nanotube TSVs for 3-D ICs 2017 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2017,
- [10] Fast and Accurate Power Distribution Network Modeling of a Silicon Interposer for 2.5-D/3-D ICs With Multiarray TSVs IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2019, 9 (09): : 1835 - 1846