Correlating reticle pinhole defects to wafer printability for the 90nm node lithography using advanced RET

被引：0

作者：

Shieh, WB ^{[1
]}

Chou, W ^{[1
]}

Yang, CH ^{[1
]}

Wu, JK ^{[1
]}

Chen, N ^{[1
]}

Yen, SM ^{[1
]}

Hsu, T ^{[1
]}

Tuan, S ^{[1
]}

Chang, D ^{[1
]}

Rudzinski, M ^{[1
]}

Wang, LT ^{[1
]}

Son, K ^{[1
]}

机构：

[1] United Microelect Corp, Hsinchu, Taiwan

来源：

OPTICAL MICROLITHOGRAPHY XVII, PTS 1-3 | 2004年 / 5377卷

关键词：

inspection; pinhole; printability;

D O I：

10.1117/12.544243

中图分类号：

O43 [光学];

学科分类号：

070207 ; 0803 ;

摘要：

For the 90nm-lithography node, understanding the impact of various reticle pinhole defects on wafer printability is essential to optimize wafer yield and to create the best quality reticle defect specification. In this study, a new programmed pinhole test reticle was designed by UMC, TCE and KLA-Tencor based on UMC's process requirements for its 193nm lithography. The reticle was manufactured and inspected on KLA-Tencor's high-resolution reticle inspection system in die to database mode by TCE. The reticle was then printed on a wafer by UMC to characterize the printability impact of programmed pinhole defects. The programmed pinhole test reticle, "193PTM", consists of two IC background patterns - poly gate and contact with programmed pinholes at various locations. The pinhole size ranges from 20nm to 75nm in 5nm increments on the wafer. By comparing the high-resolution pattern inspection results to the wafer print data, we have established the correlation and the appropriate mask specification based on wafer application guidelines.

引用

页码：1047 / 1058

页数：12

共 40 条

[31] Customized illumination schemes for critical layers of 90nm node dense memory devices in ArF lithography: comparison between simulation and experimental results
Capetti, G
Bollin, M
Pepe, A
Cotti, G
Loi, S
Iessi, U
OPTICAL MICROLITHOGRAPHY XVII, PTS 1-3, 2004, 5377 : 881 - 893
[32] Mask inspection challenges for 90nm and 130nm device technology nodes: Inspection sensitivity and printability study using SEMI standard programmed defect masks
Kim, WD
Akima, S
Aquino, C
Becker, C
Eickhoff, MD
Narita, T
Quah, SK
Rohr, P
Schlaffer, R
Tanzawa, J
Yamada, Y
22ND ANNUAL BACUS SYMPOSIUM ON PHOTOMASK TECHNOLOGY, PTS 1 AND 2, 2002, 4889 : 972 - 983
[33] Correlating scatterometry to CD-SEM and electrical gate measurements at the 90 nm node using TMU analysis
Sendelbach, M
Archie, C
Banke, B
Mayer, J
Nii, H
Herrera, P
Hankinson, M
METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XVIII, PTS 1 AND 2, 2004, 5375 : 550 - 563
[34] Reliability of air-gap Cu interconnect and approach to selective W sealing using 90nm node technology
Noguchi, J
Sato, K
Konishi, N
Uno, S
Oshima, T
Tanaka, U
Ishikawa, K
Ashihara, H
Saito, T
Kubo, M
Aoki, H
Fujiwara, T
PROCEEDINGS OF THE IEEE 2004 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2004, : 81 - 83
[35] Nano-scale dimensional focused ion beam repair of quartz defects on 90nm node alternating aperture phase shift masks
Robinson, T
Graupera, A
Morrison, T
Ramstein, M
PHOTOMASK AND NEXT GENERATION LITHOGRAPHY MASK TECHNOLOGY XI, 2004, 5446 : 384 - 401
[36] Improvement of data retention time using DRAM cell with Metallic Shield Embedded (MSE)-STI for 90nm technology node and beyond
Lee, SH
Hong, SH
Oh, JH
Choi, YK
Bae, DI
Park, SH
Roh, BH
Chung, TY
Kim, K
ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2003, : 151 - 154
[37] Thermally robust 90nm node Cu-Al wiring technology using solid phase reaction between Cu and Al
Matsubara, Y. (matsubara2@selete.co.jp), 1600, (Institute of Electrical and Electronics Engineers Inc.):
[38] New methodology for ultra-fast detection and reduction of non-visual defects at the 90nm node and below using comprehensive e-test structure infrastructure and inline DualBeam™ FIB
Schmidt, Michael B.
Kang, Hyong H.
Dworkin, Larry
Harris, Kenneth K.
Lee, Sherry F.
2006 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE AND WORKSHOP, 2006, : 12 - +
[39] High-Q on-chip inductors using thin-film wafer level packaging technology demonstrated on a 90nm RF-CMOS 5GHz VCO
Sun, X.
Linten, D.
Dupuis, O.
Carchon, G.
Soussan, P.
Decoutere, S.
De Raedt, W.
35TH EUROPEAN MICROWAVE CONFERENCE, VOLS 1-3, CONFERENCE PROCEEDINGS, 2005, : 77 - 80
[40] Advanced retrograde well technology for 90-nm-node embedded static random access memory using high-energy parallel beam
Yamashita, T
Kitazawa, M
Kawasaki, Y
Takashino, H
Kuroi, T
Inoue, Y
Inuishi, M
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2002, 41 (4B): : 2399 - 2403

← 1 2 3 4 →